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Altera_Forum
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13 years ago

Timequest output to extrernal device SDC question

I was attempting to create a SDC file to constrain my outputs but I think I do not understand the case when the FPGA drives an external device with its own clock. For the FPGA inputs I feel like I u...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Note that your clock and data will be going out very close to each other. With default analysis, this is close to a hold violation. Quite often users will invert the clock going off chip. If you do this, be sure to add -invert to the generated clock. With rbugalho's example, the default setup relationship is 10ns and hold is 0ns. If you invert the clock, then the setup relationship becomes 5ns and hold becomes -5ns.