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Altera_Forum's avatar
Altera_Forum
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13 years ago

Timequest output to extrernal device SDC question

I was attempting to create a SDC file to constrain my outputs but I think I do not understand the case when the FPGA drives an external device with its own clock. For the FPGA inputs I feel like I u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

First, you need to create a derived clock on the FPGA's clock output pin.

Then, you set the output delay constraints relative to that clock. Something like: 

create_clock -name clkin1 -period 10 
create_generated_clock -source clkin1 -name clkout1 
set_input_delay -clock clkout1 -min $minDelay 
set_input_delay -clock clkout1 -max $maxDelay

with

minDelay = -tHold - margin

maxDelay = tSetup + margin

the margin is to account for different PCB delays between the clock and the data signals