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Altera_Forum's avatar
Altera_Forum
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10 years ago

Timequest of ADCs

Hi,

My project is to deal with 5 clock asynchronous ADCs, and there are some questions while writing the sdc file. The ADC is AD9212-65MSPS, octal 10-bit serial output.

The sdc file is written as below:

# **************************************************************# Create Clock# **************************************************************

create_clock -name {adc_dco[4]} -period 3.076 -waveform { 0.769 2.307 } [get_ports {adc_dco[4]}]

create_clock -name {adc_dco[3]} -period 3.076 -waveform { 0.769 2.307 } [get_ports {adc_dco[3]}]

create_clock -name {adc_dco[2]} -period 3.076 -waveform { 0.769 2.307 } [get_ports {adc_dco[2]}]

create_clock -name {adc_dco[1]} -period 3.076 -waveform { 0.769 2.307 } [get_ports {adc_dco[1]}]

create_clock -name {adc_dco[0]} -period 3.076 -waveform { 0.769 2.307 } [get_ports {adc_dco[0]}]

create_clock -name {adc_dco_virtual[4]} -period 1.538 -waveform { 0.000 0.769 }

create_clock -name {adc_dco_virtual[3]} -period 1.538 -waveform { 0.000 0.769 }

create_clock -name {adc_dco_virtual[2]} -period 1.538 -waveform { 0.000 0.769 }

create_clock -name {adc_dco_virtual[1]} -period 1.538 -waveform { 0.000 0.769 }

create_clock -name {adc_dco_virtual[0]} -period 1.538 -waveform { 0.000 0.769 }

# **************************************************************# Set Input Delay# **************************************************************

set_input_delay -clock adc_dco_virtual[0] -max 0.3 [get_ports {adc_fco[0] adc_datain[0] adc_datain[1] adc_datain[2] adc_datain[3] adc_datain[4] adc_datain[5] adc_datain[6] adc_datain[7]}]

set_input_delay -clock adc_dco_virtual[1] -max 0.3 [get_ports {adc_fco[1] adc_datain[8] adc_datain[9] adc_datain[10] adc_datain[11] adc_datain[12] adc_datain[13] adc_datain[14] adc_datain[15]}]

set_input_delay -clock adc_dco_virtual[2] -max 0.3 [get_ports {adc_fco[2] adc_datain[16] adc_datain[17] adc_datain[18] adc_datain[19] adc_datain[20] adc_datain[21] adc_datain[22] adc_datain[23]}]

set_input_delay -clock adc_dco_virtual[3] -max 0.3 [get_ports {adc_fco[3] adc_datain[24] adc_datain[25] adc_datain[26] adc_datain[27] adc_datain[28] adc_datain[29] adc_datain[30] adc_datain[31]}]

set_input_delay -clock adc_dco_virtual[4] -max 0.3 [get_ports {adc_fco[4] adc_datain[32] adc_datain[33] adc_datain[34] adc_datain[35] adc_datain[36] adc_datain[37] adc_datain[38] adc_datain[39]}]

set_input_delay -clock adc_dco_virtual[0] -min 0.3 [get_ports {adc_fco[0] adc_datain[0] adc_datain[1] adc_datain[2] adc_datain[3] adc_datain[4] adc_datain[5] adc_datain[6] adc_datain[7]}]

set_input_delay -clock adc_dco_virtual[1] -min 0.3 [get_ports {adc_fco[1] adc_datain[8] adc_datain[9] adc_datain[10] adc_datain[11] adc_datain[12] adc_datain[13] adc_datain[14] adc_datain[15]}]

set_input_delay -clock adc_dco_virtual[2] -min 0.3 [get_ports {adc_fco[2] adc_datain[16] adc_datain[17] adc_datain[18] adc_datain[19] adc_datain[20] adc_datain[21] adc_datain[22] adc_datain[23]}]

set_input_delay -clock adc_dco_virtual[3] -min 0.3 [get_ports {adc_fco[3] adc_datain[24] adc_datain[25] adc_datain[26] adc_datain[27] adc_datain[28] adc_datain[29] adc_datain[30] adc_datain[31]}]

set_input_delay -clock adc_dco_virtual[4] -min 0.3 [get_ports {adc_fco[4] adc_datain[32] adc_datain[33] adc_datain[34] adc_datain[35] adc_datain[36] adc_datain[37] adc_datain[38] adc_datain[39]}]

The question is that whether the Quartus II will make some relationship between clocks: adc_dco[0], adc_dco[1], adc_dco[2], adc_dco[3], and adc_dco[4]. Shold I write some constraints to separate them? In actual situation, there is no relationship between them.

Thank you!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    If there are no paths where one adc_dco clock feeds the source and a different adc_dco clock feeds the destination, then it doesn't matter. You could cut timing between them but you're not actually cutting any paths in the design.

    Some users don't cut paths like this, in which case if they mistakenly create a path between these clock domains, it will fail timing. That works pretty well when they are different frequencies, but Quartus will create a 3.076 setup relationship between these clocks by default, so a mistaken path could actually pass timing. A user could shift the clocks a little to try and get a bad relationship, but that is kind of a pain too.

    But if you do have paths going between these domains and your logic handles them asynchronously, then yes, they should be cut. I assume adc_do feeds a PLL, so it's the output of the PLL that you probably want to cut, i.e. something like:

    set_clock_groups -asynchronous -group {adc_dco[0] adc_dco0_pll_long_name|clk[0]}

    -group {adc_dco[1] adc_dco1_pll_long_name|clk[0]}

    -group {adc_dco[2] adc_dco2_pll_long_name|clk[0]}

    -group {adc_dco[3] adc_dco3_pll_long_name|clk[0]}

    -group {adc_dco[4] adc_dco4_pll_long_name|clk[0]}
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thanks for your clear explanation, and I see.

    In my project, there are no paths going between these clock domains.

    That's all.