Timequest of ADCs

If there are no paths where one adc_dco clock feeds the source and a different adc_dco clock feeds the destination, then it doesn't matter. You could cut timing between them but you're not actually cutting any paths in the design.

Some users don't cut paths like this, in which case if they mistakenly create a path between these clock domains, it will fail timing. That works pretty well when they are different frequencies, but Quartus will create a 3.076 setup relationship between these clocks by default, so a mistaken path could actually pass timing. A user could shift the clocks a little to try and get a bad relationship, but that is kind of a pain too.

But if you do have paths going between these domains and your logic handles them asynchronously, then yes, they should be cut. I assume adc_do feeds a PLL, so it's the output of the PLL that you probably want to cut, i.e. something like:

set_clock_groups -asynchronous -group {adc_dco[0] adc_dco0_pll_long_name|clk[0]}

-group {adc_dco[1] adc_dco1_pll_long_name|clk[0]}

-group {adc_dco[2] adc_dco2_pll_long_name|clk[0]}

-group {adc_dco[3] adc_dco3_pll_long_name|clk[0]}

-group {adc_dco[4] adc_dco4_pll_long_name|clk[0]}