Timequest makes timings but not the real stratix IV hardware

I am having problems making actual timings on the real hardware. I'm actually trying to upgrade from a stratix III to a stratix IV. The design works on a stratix III.

After I've set up a basic constraint file (.sdc), I see Timequest properly identifying my main clocks and telling me that I'm making timings with no problem. Yet my stratix IV hardware still isn't making timings. I can use the signaltap to see how some of my waveforms at some particular point begin to contain glitches like distortions. These glitches only appear as I am integrating more and more things into the FPGA. So the problems begin only as the chip uses more resources and consumes more current. Also, I can usually improve the distorted signal as I cool the chip with an anti-static freezer.

I don't know what to do because according to timequest, my Fmax is well above what I need, e.g., 149MHz when I need only 120Mhz, and 312Mhz when I need only 240 Mhz.

I should also mention that this is a multi-rate design. There is a main clock but actual data rates are controlled by toggling the clock enable of the registers. Now, I haven't declared any multi-cycle paths in the constrained file, however, I would have expected in this case that this would be an issue only if I had not made timings.

Any suggestions?