TimeQuest Issue with wrong launch clock & wrong latch edge

In my VHDL code, I use rising_edge for shift registers to latch data.

But TimeQuest report timing of these shift registers using falling edge of clock.

What's wrong?

pls see the detailed VHDL code below:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
entity FreqMeasure_ADReader is
	
	port
	(
	   IN_AD_SCLK     : in std_logic;
	   IN_TARGET_SIGNAL  : in std_logic;
	   IN_AD_DATA	      : in std_logic;
	   OUT_AD_SCLK	      : out std_logic;
      OUT_AD_VALUE      : out integer		
	);
   constant c_AD_RESOLUTION : integer :=16;
end entity;
architecture register_ad_sclk of FreqMeasure_ADReader is
   component SynSignalGenerator_CrossingClockDomain is
      port
	   (
	      IN_CLK      : in std_logic;
		   IN_STROBE	  : in std_logic;
		   OUT_SYN_SIGNAL    : inout std_logic
	   );
	end component;
	
	signal   s_ad_sdata_shift_reg   : std_logic_vector(c_AD_RESOLUTION-1 downto 0);
	signal   s_ad_sclk_enable :std_logic;
	signal   s_ad_sclk :std_logic;
	signal   s_counter :integer range c_AD_RESOLUTION*2 downto 0;
	signal   s_target_signal : std_logic;
	signal   s_counter_synclear : std_logic;
begin
 	           
s_target_signal <= NOT IN_TARGET_SIGNAL;
counter_synclear_gen: SynSignalGenerator_CrossingClockDomain PORT MAP(IN_AD_SCLK, s_target_signal, s_counter_synclear);
sclk_en_gen: process(IN_AD_SCLK, s_counter_synclear)
             begin
                 if(s_counter_synclear = '1') then
                     s_counter <= 0;
                 elsif(rising_edge(IN_AD_SCLK)) then
                     if(s_counter = 1) then
                         s_ad_sclk_enable <= '0';
                         s_counter <= s_counter + 1;
                     elsif(s_counter < c_AD_RESOLUTION * 2) then
                         s_ad_sclk_enable <= '0';
                         s_counter <= s_counter + 1;
                     else
                         s_ad_sclk_enable <= '1';
                     end if;
                 end if;
             end process;
ad_sclk_gen: process(IN_AD_SCLK, s_ad_sclk_enable) 
               begin
                   if(s_ad_sclk_enable = '0') then
                      if(rising_edge(IN_AD_SCLK)) then
                          s_ad_sclk <= NOT s_ad_sclk;
                      end if;
				   else
					  s_ad_sclk <= '1';	
                   end if;
               end process;
OUT_AD_SCLK <= s_ad_sclk;
shift_reg_0: process(s_ad_sclk)
               begin
				     if(rising_edge(s_ad_sclk)) then
					     s_ad_sdata_shift_reg(0) <= IN_AD_DATA;
				     end if;
               end process;
                                       
shift_reg_gen: for i in 1 to s_ad_sdata_shift_reg'high generate
                  process(s_ad_sclk)
                  begin
					    if(rising_edge(s_ad_sclk)) then
						    s_ad_sdata_shift_reg(i) <= s_ad_sdata_shift_reg(i-1);
					    end if;                  end process;
               end generate;
OUT_AD_VALUE <= CONV_INTEGER(s_ad_sdata_shift_reg);
end register_ad_sclk;

Pls see the following TimeQuest screen shot pic:

http://blogimg.chinaunix.net/blog/upfile2/080124210233.jpg

Another question:

I create AD_SCLK for *|FreqMeasure_ADReader:*|s_ad_sclk, pls see below

create_generated_clock -name AD_SCLK -source FreqMeasure_NiosII:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2 -divide_by 2 

And TimeQuest report timing of *|FreqMeasure_ADReader:*|s_ad_sclk with wrong launch clock, the launch clock should be FreqMeasure_NiosII:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2.

Pls note that: *|FreqMeasure_ADReader:*|s_ad_sclk is a toggle register launch & latch by FreqMeasure_NiosII:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2, which make TimeQuest confused.

How can I correct TimeQuest to report correct timing in this case?

Pls also see the following screen shot pic:

http://blogimg.chinaunix.net/blog/upfile2/080124210633.jpg