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Altera_Forum's avatar
Altera_Forum
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18 years ago

TimeQuest Issue with wrong launch clock & wrong latch edge

In my VHDL code, I use rising_edge for shift registers to latch data. But TimeQuest report timing of these shift registers using falling edge of clock. What's wrong? pls see the detailed VH...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I have look into technology post-fitting view, and found that the shift register I mentioned before was driven by falling edge of pll|clk2. So the TimeQuest report is right.

But I VHDL code is using

--- Quote Start ---

if(rising_edge(s_ad_sclk)) then

s_ad_sdata_shift_reg(i) <= s_ad_sdata_shift_reg(i-1);

end if;

--- Quote End ---

And What I want is rising_edge, what I can do?

Also, pls don't forget my senond question described above.

Thanks!