--- Quote Start ---
Hi Rysc:
Thanks for you reply!
I can deal with this issue use two kinds of constrain.
The first constrain is as below, which just setting false paths constain.
set_false_path -from [get_registers {*tdc_ctrl_set[0]}] -to [get_clocks {inst|altpll_component|pll|clk[2]}]
The second constrain is as below, which just setting multi-cycle paths constrian.
set_multicycle_path -from [get_clocks {inst|altpll_component|pll|clk[0]}] -to [get_clocks {inst|altpll_component|pll|clk[2]}] -end -setup 4
set_multicycle_path -from [get_clocks {inst|altpll_component|pll|clk[0]}] -to [get_clocks {inst|altpll_component|pll|clk[2]}] -end -hold 3
My question is whether TimeQuest doesn't permit customer using multi-cycle path constrain when two clocks frequency aren't interal times relationship, like my case is (250/100) 2.5 time?
--- Quote End ---
The purpose of any design is to pass timing rather than get a reported timing pass. You cannot freely apply deconstraints unless applicable to your case.
To apply false path is applicable if you don't care about sampling your signal correctly at first edge. Then you may decide to use synchronisers to pick it up after one or two sampling attempts(double synchronisers). This could be the case of a signal that changes occasionally.
Similarly, multicycle is decided by you the designer after you decide which edge launches to which latch according to your logic and if it turned out that you have 2 or more minimum clocks in between (and always) then you can apply multicycle of 2.
Honored Contributor
