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Altera_Forum
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13 years ago --- Quote Start --- From your picture, which edge do you want launching(and what's it's time) and which edge is latching(and what's it's time)? You can usually get it with multicycles. That being said, I had a case where the conditions really weren't possible. Note that set_max_delay will override the setup relationship with whatever number you want, so it will do what you want. --- Quote End --- Hi Rysc: Thanks for you reply! I can deal with this issue use two kinds of constrain. The first constrain is as below, which just setting false paths constain. set_false_path -from [get_registers {*tdc_ctrl_set[0]}] -to [get_clocks {inst|altpll_component|pll|clk[2]}] The second constrain is as below, which just setting multi-cycle paths constrian. set_multicycle_path -from [get_clocks {inst|altpll_component|pll|clk[0]}] -to [get_clocks {inst|altpll_component|pll|clk[2]}] -end -setup 4 set_multicycle_path -from [get_clocks {inst|altpll_component|pll|clk[0]}] -to [get_clocks {inst|altpll_component|pll|clk[2]}] -end -hold 3 My question is whether TimeQuest doesn't permit customer using multi-cycle path constrain when two clocks frequency aren't interal times relationship, like my case is (250/100) 2.5 time?