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Altera_Forum's avatar
Altera_Forum
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13 years ago

TimeQuest issue need you help

There are two clock domains in my project, one is 100MHz, another is 250MHz. There are some time issue after full compilation as attached file shows. The issue is caused by one signal from 100MHz to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

From your picture, which edge do you want launching(and what's it's time) and which edge is latching(and what's it's time)? You can usually get it with multicycles.

That being said, I had a case where the conditions really weren't possible. Note that set_max_delay will override the setup relationship with whatever number you want, so it will do what you want.