TimeQuest: How do I eliminate the clock delay through a PLL from my timing budget for external IO?

Maybe it's best if I use an example:

Assume a clock delay of 9ns from the originating clock to the registers.

I want the data path to be between 6 and 7 ns both from the register to the IO pad and from the IO pad to the register (bi-directional data).

From my experimentation, it looks like on the output, you add the clock and data paths for the max delay and subtract the clock path from the data path on the min delay, but it doesn't seem to work all the time and I have no idea what the tool is doing.

So my question is for the above example, how do i write the set_max/min_delay constraints for both the output and the input?

Thanks