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CBehr's avatar
CBehr
Icon for New Contributor rankNew Contributor
7 years ago

TimeQuest: How do I eliminate the clock delay through a PLL from my timing budget for external IO?

I've got the following related constraints: set_clock_groups -asynchronous -group {input_clk_40} \ -group {pll_output_clk_50|Frac_PLL(eg.)} -group {pll_output_clk_50|divclk} create_clock -name vi...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

For clock path, you can either select a compensation mode (eg, normal mode) or set a phase shift. I could not understand the following. Can you elaborate?

How do I constrain a range of delay from the clock input of a register to the output pad of a register without ? When I try, the tool misinterprets that as the delay from the input clock (which is unrelated to a single register in the entire hardware design) to the output pad.

Thanks