TimeQuest: How do I eliminate the clock delay through a PLL from my timing budget for external IO?

Thanks, but that's no help.

This is an asynchronous device. There is no timing related to any clock. The timing is related from output to input and vice versa. I've searched on this and no-one seems to have a accepted solution to the async bus so I need the constraints to be simple.

Maybe I can make the question simpler: How do I constrain a range of delay from the clock input of a register to the output pad of a register without ? When I try, the tool misinterprets that as the delay from the input clock (which is unrelated to a single register in the entire hardware design) to the output pad. Same thing for pad to register input. Is there something I'm missing? I've been reading through Ryan Scoville's guide and I'm not seeing an answer.

If anybody else has dealt with this, any suggestions in the right direction would help.

Thanks again.