TimeQuest: How do I eliminate the clock delay through a PLL from my timing budget for external IO?

You should not be isolating the input clock from the PLL outputs like this. You don't need that set_clock_groups command at all, assuming Frac_PLL and divclk are synchronous to each other and coming from the same PLL. Use a compensation mode in the PLL IP parameters to compensate for clock path delay, including through the PLL.

Also, your set_output_delay values should not be 0. They should accurately reflect the maximum and minimum external delays to the "downstream" device to guarantee meeting that device's setup and hold timing requirements.