Timequest Help needed for proper analysis

The attached failing path is a minimum pulse width, which isn't do to a 3.9ns clock delay. It comes directly from your 2.941ns clock period. What device and speed grade are you targeting? It looks like the memory is only able to run at (1/(2*1.597) = 313MHz, while you're trying to run it faster. (The requirement is not really the clock period, but a minimum high and low time, which is more relevant if your duty cycle isn't 50/50.) But it sounds like your running into a spec'd limit. The Globals, Memories, I/O and possibly other hard components have maximum rates they can run at, even if the micro-timing analysis says it can run faster. A common example is if your clock domain were two registers and nothing else. From a static timing analysis, they may only have a 1ns data delay, so they could technically run at 1GHz, but the global clock tree could never toggle that fast for capacitive and other reasons, so you would get a min pulse width error.