TimeQuest found "Unconstrained Paths"

Finally it works ... in sense that there is no more unconstrained paths.

Well, TimeQuest reports timing violations, but this is another story.

Here below - modified .sdc.

If I properly understood your last message, you agree that for my case virtual clock is irrelevant ?

create_clock -name clk -period 20 [get_ports clk]

create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}

derive_pll_clocks

derive_clock_uncertainty

set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]

set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]

set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]

create_generated_clock -name clk_ext_sdram -source [get_pins {u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] [get_ports {sdram_clk}]

set_false_path -to [get_ports {sdram_clk}]

# Constraint SDRAM DATA for input

set_input_delay -clock clk_ext_sdram -max 0 [get_ports sdram_dq[*]]

set_input_delay -clock clk_ext_sdram -min 0 [get_ports sdram_dq[*]]

# Constraint SDRAM DATA for output

set_output_delay -clock clk_ext_sdram -max 0 [get_ports sdram_dq[*]]

set_output_delay -clock clk_ext_sdram -min 0 [get_ports sdram_dq[*]]

# Constraint DRAM ADDRESS for output

set_output_delay -clock clk_ext_sdram -max 0 [get_ports sdram_addr[*]]

set_output_delay -clock clk_ext_sdram -min 0 [get_ports sdram_addr[*]]

# Constraint SDRAM Controlss for output

set_output_delay -clock clk_ext_sdram -max 0 [get_ports {sdram_bank[*] sdram_dqm* sdram_cas_n sdram_ras_n sdram_cke sdram_cs_n sdram_we_n}]

set_output_delay -clock clk_ext_sdram -min 0 [get_ports {sdram_bank[*] sdram_dqm* sdram_cas_n sdram_ras_n sdram_cke sdram_cs_n sdram_we_n}]

set_false_path -from [get_ports sw*]

set_false_path -from [get_ports key*]

set_false_path -from * -to [get_ports led*]

set_false_path -from * -to [get_ports hex*]