Forum Discussion
Altera_Forum
Honored Contributor
8 years ago --- Quote Start --- but "generated clock" is already created by the command derive_pll_clocks. --- Quote End --- with derive_pll_clocks command you have created clocks for PLL output pins. In addition as I suggested you will create clock for clock out pin which drives SDRAM. Your clock tree should look something like this: PLL input clock| -PLL output C0| [/INDENT] -PLL output C1|[/INDENT] -CLK ext|[/INDENT][/INDENT][/INDENT] By using CLK ext you will constrain your output relative to actual clock which drives SDRAM. As for input constrains you are right. You should use same CLK ext clock.