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Altera_Forum's avatar
Altera_Forum
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18 years ago

TimeQuest constraints relative reference pin

I am beginner with TimeQuest.

There is a difficulty with describing constraints for SPI (Serial Peripheral Interface) accommodated in FPGA.

SPI comprises three units for generating serial-data-output (sdout), serial-clock (spiclk) and serial-data-input (sdinp) signals. All units are clocked by the same system clock in FPGA. spiclk signal is derived from the system clock by dividing by four and enabling only during data transfers.

The second external member of SPI channel has setup (4ns), hold (1ns) and clock to output (20ns) times relative its input serial clock – spiclk.

I am not worry about the system clock to spiclk output delay.

It would be to describe the SPI constraints relative spiclk directly like follow incorrect commands:

set_output_delay -clock system_clock -reference_pin [get_ports spiclk] -max 4.000 [get_ports sdout]

set_output_delay -clock system_clock -reference_pin [get_ports spiclk] -min -1.000 [get_ports sdout]

set_input_delay -clock system_clock -reference_pin [get_ports spiclk] 20.000 [get_ports sdinp]

What are correct commands?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The idea is good, but timequest does not take functional information into consideration, and therefore this won't work.

    One possible solution would be to declare spiclk as a clock, but because the signals are not registered by that clock I think it would not work.

    Anybody has any other ideas ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Here is how I went about a similar issue.

    My SPI controller operates at a 2x, or, 4x clock & generates the 3 control outputs including the clock pin, and, the 3 outputs have a 1 additional DFF driving the pin with fast-output-enable on. The data input pin has 1 additional DFF latch at the input with fast input enable on.

    Now this might require a little addition to your control logic, however, every time you compile your design, no matter which speed grade of FPGA, the pin-pin clk difference of the IOs will only differ in the pico-second range. You will get improved IO noise and timing immunity. Timequest will only be concerned about your logic F-Max being achieved up until the IO DFF.

    The cons are that your design will at least consume 4 additional logic cells. SPIs with a 4 bit bus will eat 11 logic cells. You need at least a 2x internal logic clock compared to the SPI clock you wish to achieve. There will be an additional 2 series clock delay in you SPI driver's data valid output.