TimeQuest constraints relative reference pin

Here is how I went about a similar issue.

My SPI controller operates at a 2x, or, 4x clock & generates the 3 control outputs including the clock pin, and, the 3 outputs have a 1 additional DFF driving the pin with fast-output-enable on. The data input pin has 1 additional DFF latch at the input with fast input enable on.

Now this might require a little addition to your control logic, however, every time you compile your design, no matter which speed grade of FPGA, the pin-pin clk difference of the IOs will only differ in the pico-second range. You will get improved IO noise and timing immunity. Timequest will only be concerned about your logic F-Max being achieved up until the IO DFF.

The cons are that your design will at least consume 4 additional logic cells. SPIs with a 4 bit bus will eat 11 logic cells. You need at least a 2x internal logic clock compared to the SPI clock you wish to achieve. There will be an additional 2 series clock delay in you SPI driver's data valid output.