[TimeQuest] constrain path between clock domain

Thanks for your reply.

J_k you're right, in a new design it is changed. In the existing, this is not possible.

Rysc:

In most transitions a FIFO or Data_valid signal is used. For these transitions synchronization chains are used to avoid metastability problems.

An exact equal delay is not necessary. And I know that this can not be achieved.

My problem is that, without limitation, the times between different translations are very different.

The receiver clock is higher than the transmitter clock. Therefore, the difference can be greater than one receiver clock cycle, but must be less than 2 clock cycles. In some translation it is more than 3 cycles delay.

I will use set_min / max delay and skew assignment trying to minimize this difference.

All other paths between the clock domain should be set individually as false path?