[TimeQuest] constrain path between clock domain

What do you mean by equal? Within 100ps of each other? 10ns? When I've been asked similar questions, the user just means they don't want them too far from each other, but don't really know what that is. Try to think of what a failure looks like, i.e. if one is 10ns and another path is 3ns, how would that actually fail in hardware? Becuase they're asynchronous, they could be off by a whole clock cycle.

And remember that being asynchronous transfers, the latching register could always go metastable. Are you handling that too?

Most systems try to limit transfers between domains to a core point, transfer everything over with a FIFO, and then continue in the other domain. It may be a wide data path and lots of control signals, but it's all done with the same FIFO.

Finally, I would recommend a skew constraint. I have seen some users not use set_clock_groups and instead do something like:

set_max_delay -from [get_clocks A] -to [get_clocks B] 10.0

set_min_delay -from [get_clocks A] -to [get_clocks B] -5.0

This does include clock skew in the calculation(which I would argue is correct), but gives a range. I'm not a huge fan of it, but get it.