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For my design, when I check TimeQuest: Tasks->Diagnostic->Check Timing, I get one entry on "Clock Assignments on Output Ports". It's for the output of a PLL that is fed directly out of the FPGA as the encode clock to an external FPGA. This net routes to nowhere else in the FPGA. I've identified the port as a created clock in my sdc file.
What is TimeQuest trying to warn me about here? Is it hinting that I might want to handle outputing the clock differently? Is there some other (better?) way to handle sending generated clocks out of the FPGA?
Thanks!
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You want to use a create_generated_clock assignment on the output port, not a create_clock. This is especially important if you want to use that clock for example in a source synchronous output interface. The source of the generated clock should be the output pin name of the PLL that is driving the clock to the output port. The reason you want to use a generated clock is so that the timing between the output clock and any data that you might be clocking out of the device (again for example in a source synchronous output interface) can time back to a common point; the input to the PLL so the two can be related in the report_timing report. If you put a create_clock constraint on the output port, then the timing begins from that point as is the case with all absolute clock assignments. Of course if you are not trying to time anything in your design with this output clock, then you can ignore this warning in the Check Timing report.
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