Forum Discussion
NuvKFC
Contributor
ContributorTimeQuest can't analysis the clock from the PLL
The problem is as follows.
I need a MUX to switch the clock between normal mode and test mode. And I don't care about any transient state when clock switching.
The ending shows the design. 'pll_...
Hi SyafieqS_Intel, finally, I use the command, /*synthesis keep */, to keep relative port so that TimeQuest can find the CLK[4] port of the PLL.
The CLK[4] port of the PLL in post-fit is "pll|altpll_component|auto_generated|pll1|clk[4]". Thank you, SyafieqS_Intel, very much.
SyafieqS
Super Contributor
Super ContributorI’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
NuvKFCContributor
ContributorHi SyafieqS_Intel, OK, no problem,. Thank you very much.
