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Altera_Forum
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15 years ago

TimeQuest Asynchronous Interface Constraints

Hi, I have been through a lot of online material with nothing that seems to shed light on my query (or I'm just not getting it.) I have a CPLD design I want to constrain properly using the...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Thanks for that link Pancake, it's quite an in depth PDF which I've just read. Like most of the other documentation I've read it doesn't really say that pure asynchronous signals entering a chip should be set as false paths, (assuming they are handled properly by the designer -double/ triple flopping).

It does make sense that they should, it's just you don't want to cut timing from the analysis without some kind of confirmation that's how it's done.

Thanks for the feedback.