TimeQuest Asynchronous Interface Constraints

Asynchronous signals that are input to the FPGA feeding synchronizers are typically constrained with false path statements in SDC. Less commonly, one could constrain them with set_multicycle_path constraints instead. If you were coming from the Xilinx world and are used to their methodology, then you could use set_max_delay constraints between the rising edge of the clocks. As I said though, most people cut the path with set_false_path statements. If you are concerned about the metastability issue, this can also be analyzed in Quartus II software.