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Altera_Forum's avatar
Altera_Forum
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13 years ago

TimeQuest and gate leve simulation incongruity

Hi guys!

I have a problem regarding a gate-level simulation. In order to isolate the problem I compiled and synthetised a design with a single FF.

I can't figure out whether it is due to wrong settings in Time Quest or in Modelsim.

I upload the project.

To summarise, I don't have any problem neither in compilation, nor in functional simulation, nor in Time Quest.

When I run the gate level simulation, I clearly see that the output doesn't follow the input after the latch edge but (sometimes) it does it after 1 clk cycle.

Has anybody an idea about the reason for that happens?

Thank you in advance,

Marco

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    You could be looking at normal timing behaviour of lauch/latch. Compared to functional simulation the data transition will occur somewhere before next clock edge or even further in case of multicycle deconstraint.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thank you for your answer,

    my evidence is:

    1) the design is just a FF (no multicycle constraits). it has been simplified in order to isolate the problem)

    2) after compilation, TQ says that Fmax = 130 MHz (my design runs @ F = 125 MHz and non violations are detected by TQ)

    3) functional simulation (obviously) works perfectly

    then: expected behaviour:

    The output (q) is expected to follow the input (d) in a time within the launch edge and the latch edge

    but: observed behaviour (in gate-level sim)

    The output (q), sometimes (NOT always) follows the input (d) after the latch edge

    Thank you