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Altera_Forum
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13 years ago

TimeQuest and gate leve simulation incongruity

Hi guys! I have a problem regarding a gate-level simulation. In order to isolate the problem I compiled and synthetised a design with a single FF. I can't figure out whether it is due to wro...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You could be looking at normal timing behaviour of lauch/latch. Compared to functional simulation the data transition will occur somewhere before next clock edge or even further in case of multicycle deconstraint.