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Altera_Forum
Honored Contributor
13 years agoThank you for your answer,
my evidence is: 1) the design is just a FF (no multicycle constraits). it has been simplified in order to isolate the problem) 2) after compilation, TQ says that Fmax = 130 MHz (my design runs @ F = 125 MHz and non violations are detected by TQ) 3) functional simulation (obviously) works perfectly then: expected behaviour: The output (q) is expected to follow the input (d) in a time within the launch edge and the latch edge but: observed behaviour (in gate-level sim) The output (q), sometimes (NOT always) follows the input (d) after the latch edge Thank you