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Altera_Forum's avatar
Altera_Forum
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13 years ago

Timequest and Async Paths

Hello: I have a simple CPLD design that has an async input pin that goes to a latch. From the latch it goes to an async output pin. I would like to constrain the input path from the pin to the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I'm not really getting your goal...

Is the source of AsyncIn really asynchronous to the clock?

Is the destination of AsyncOut really asynchronous to the clock?

And if so, what is the purpose of the clocked logic?

BTW, trying to constrain a delay to be excatly X ns is not possible due to PVT variations. You can only constrain to a range.