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Altera_Forum's avatar
Altera_Forum
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18 years ago

TimeQuest Analyzer

Following I have some questions to TimeQuest Timing Analyzer!

1. How can I change the name from the generated clock’s?

TimeQuest doesn’t accept the changes I done in Edit Clock Constraints

2. Are PLL outputs always generated clocks?

3. Are PLL inputs always base clocks?

4. TimeQuest found other base clocks than the PLL input clocks. TimeQuest assigned the clock “sclk” (8MHz) for an external SPI interface as base clock with a frequency from 1GHz. I generated the sclk clock, with a counter, from a generated clock (PLL output 48MHz).

Why does TimeQuest assign this clock as base clock and how can I delete this one?

Tks!:

:)

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I think the following should answer most if not all of your questions.

    1. Create a new SDC file named <something>.sdc

    2. Add the following two lines to the SDC file:

    derive_clocks -period 10.000

    derive_pll_clocks

    These two lines will derive all base clocks and give them a 100Mhz constrain. It will also derive all PLL clocks in your design.

    3. Add this SDC file to your project.

    4. Open TimeQuest and run "Update Timing Netlist"

    5. Now at the command prompt type "write_sdc -expand <something>.sdc

    6. Now you can open <something>.sdc and change the generated clock names and change the frequency of all the base clocks.

    Note your new SDC file now has to be manually changed every time you change a setting in the PLL MegaWizard files that effects timing.

    Have fun.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I tend to recommend keeping the derive_pll_clocks command in my .sdc, but never keep derive_clocks. The only downside with derive_pll_clocks is that you get stuck with the long clock name it uses. But you quickly get to recognizing them, and the benefits of having derive_pll_clocks generally outweighs this one downside.

    But most importantly, once you have an .sdc file, never let TimeQuest overwrite it. It should be your file that you enter constraints into. If you ever have TimeQuest write out .sdc constraints, write them to a junk.sdc file and then cut and paste into your file.

    If you like the TQ GUI for entering constraints, note that when you have your .sdc file open, you can go to Edit -> Enter Constraint, and access the same constraint GUIs, it just enters the text into your .sdc file directly. (I don't mind it entering a constraint, just not overwriting the whole thing.)

    PLL outputs are always generated clocks. The inputs are not always base clocks. You could have a PLL feed another PLL, so the second PLL's output is a generated clock whose source is the output of the first PLL, i.e. another generated clock.

    If sclk is a register in your design used as a clock, you will want to apply a generated_clock to it. Ripple clocks always need this. Derive_clocks will assign a base clock to the register which is generally wrong(but it can't assign a generated clock to it either, since it has no idea if that register creates a divide_by 2, divide_by 4, or whatever frequency. So you need to manually do this since you know what the new clock will be.)