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Yes, it is possible if you are lucky with the fitter. Particularly easy with DDR interface when data and clock are generated with same delay.
The question is why should the output data and clock be dead edge aligned?
You better set delay according to destination register of external device.
ignoring board differences of data/clk delay then you should set
maximum delay = Tsu of external register and
minimum delay = hold time of external register.
The fitter hopefully will then insert the required delay.
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do I get to know the Tsu and Thd of the external register? it is a fixed value?
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