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Altera_Forum
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15 years ago

Timequest / virtual clock

Altera recommends in the Quartus Handbook to use virtual clock if you model external delays in conjunction with clock uncertainty. I am analyzing a small design were the external chips and the f...
Altera_Forum's avatar
Altera_Forum
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15 years ago

David,

That is what I tried to say in my last posting. I get this two different timing results if I only change the SDC file and do the analysis without recompilation (same synthesis, place and route). This is really strange ...