Timequest & source-synchronous DDR output problem

Hi all,

I have the following construction:

- A databus, constructed wit DDR output flipflops (DataOut(15 downto 0))

All these DDR flipflops are clocked with ClkInternal.

- A clock, constructed with a DDR output flipflop with its input_h tied to logic1 and its input_l tied to logic0. The DDR output flipflop is used as a 'clock mirror' (the output signal is called ClkOut). This DDRflipflop is generated with ClkInternalPh90.

Externally I have a device that requires:

- tSetup for DataOut referred to ClkOut is 1ns.

- tHold for DataOut referred to ClkOut is 2ns.

How should I constrain this in Timequest?

I hope somebody can help.

Thanks and best regards,

Karel D