Timequest & Output delay problem

Calvyn:

The answer could be yes but it assumes that the model you use has an external clock that drives both the external device and the FPGA. This is shown in the Timing Analyzer Cookbook example (figure 1-9)

That is not the case in my design.

I have an external oscillator which drives the external device. The external device then drives the clock into the FPGA (this is usually referred to as source synchronous).

Because of this I have added the clock delay from the external device to the FPGA. Normally you would then subtract the min delay for the clock (if this is for the max output constraint) to the external device but in my case I have set this to zero because as I mentioned above the external device is sourcing the clock to the FPGA.

Hope this helps.

Alan