Timequest & Output delay problem

I've found it easy to totally get wrapped up into equations and lost in the details. THe funny thing is there is no complex math, it's just addition or subtraction. So I start with my requirement and I figure out that the -max output delay cuts into it as it gets larger. So anything that cuts into my setup is added, anything that helps is subtracted.

Most importantly though, is analyzying the final report. I tend to look at the Data Path tab rather than the waveform because it gives more details, but in the end they show the same thing. For an output, the Data Arrival is the delay through the FPGA. This is everything you care about except a) manual PLL phase-shifts or b) negative edge clocking, both of which affect the launch and/or latch edge. So in your case which doesn't have a) or b), I would treat it as the Tco. Your requirement is 20.833. That requirement minus your output delay and minus your Tco should be your slack, and it should all add up.