Timequest & Output delay problem

Which example?

Walking thru it, your clocks are edge aligned, so the default setup relationship is one clock period, or 20.833ns. This is the difference between your launch and latch edge. If your external delay was 0ns(and I often start them at 0ns for a placeholder), then the FPGA has 20.833ns to get it's data out. Now, whatever the external delay is will cut into that delay. So as the external delay gets larger, the FPGA has less time to get the data out.

So the Tsu should be a positive number. The board delay is also a positive number. The clock delay to the FPGA is a positive number. All three of these things hurt setup and help hold. The only one that helps setup is the board delay to the external device, and hence that's a negative number.