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Altera_Forum
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13 years ago

Timequest - SSO generated output clocks

Hi all,

I'm having some confusion around a source synchronous output that I'm trying to constrain. I have a data_out bus which is clocked out by a clock generated by a PLL in my FPGA. I pass this clock out along with the data via a DDIO component which essentially inverts it to try and place it near the centre of the data valid window. (FYI The DDIO component is just two registers set to 1 and 0 that are muxed by the PLL clock to produce a 0 when the clock is a 1 and a 1 when the clock is a 0.)

When constraining this, I wanted to create a generated clock at my output port from which to specify my delays. Initially I specified the source of this clock as the output pin of the DDIO component and the target as my clk_out port but this doesn't seem to result in the clock being created (no errors or warnings produced but the clock does not appear in my clocks report).

create_generated_clock -name nclk -source ddio_outa|dataout get_ports clk_out

Alternatively, I have specified the source as the mux input of my DDIO block (the PLL clock) and the target as the clk_out port. This does create the clock, but Timequest does not seem to realise that the clock is inverted by the DDIO block so it looks like a perfect copy of the PLL clock.

create_generated_clock -name nclk -source ddio_outa|muxsel get_ports clk_out

Obviously, I can just force the clock to be an inversion of the PLL clock with the inclusion of -invert but surely this will create a perfect invertsion of PLL clock which does not take into account the tco of the registers in the DDIO component (i.e. there will be a slight phase shift between my PLL clock and my inverted PLL clock). I would really like the timing analyser to be able to work out the delays between the signals rather than me having to tell it!

I have noticed similar examples of using registers as clock dividers but in these examples the generated clock is manually specified as -divide_by 2 which again must neglect to take into account the delays through the register.

Can anyone suggest the correct way to specify this clock?

Many thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    You need to create a generated clock that has the PLL output as the source and the clock output pin of the FPGA as the target. Then, constrain your I/O relative to this generated clock. Don't add any manual delays or inversions between the PLL and the output pin. Instead, use the PLL configuration to get the correct timing and phase.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks TrueBlue, that certainly is a valid alternative method for setting up a source synchronous bus although it is more demanding of pll resources and potentially has more variability from compile to compile (the delay between the PLL output and the pin).

    Assuming that I didn't want to change the way that the output clock was generated, I am still interesting in knowing how one would define an output clock that it is derived from a register output.

    Perhaps the output_delay timing model is not suitable in this instance and I would be better served just treating the clk_out as a signal and constraining the max skew between the databus and the clk_out (if the clock DDIO component is in an IO cell and all of the data bits are in IO cells then their tcos should be pretty well defined and close together?). There would be no generated output clock or concept of Tsu and Th relative to this. But if the clk_out is sent off chip with a minimum of skew relative to the data then can I therefore infer that I have a timing window of "Tperiod - 2*Tskew"?

    Alternatively, I have seen the reference_pin command used but I wasn't very successful in implementing this...
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Your DDIO component will be reduce to a simple inverter, as the registers have constant outputs.

    Even if it weren't, the registers uTco would not have an impact in timing, as the register's outputs are constant.

    Drop the DDIO component and use a simple inversion to get an inverted clock at clk_out.

    TimeQuest does know to account for propagation delay in clocks.

    You just need to use "create_generated_clock -source $pllClockOut -invert [get_ports clk_out]" and it will correctly account for the delay between the PLL and the FPGA pin.

    BTW, your syntax for creating a derived clock was wrong. The -source parameter must be a clock, not a net/register/pin/port.