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Altera_Forum
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13 years ago

Timequest - SSO generated output clocks

Hi all, I'm having some confusion around a source synchronous output that I'm trying to constrain. I have a data_out bus which is clocked out by a clock generated by a PLL in my FPGA. I pass t...
Altera_Forum's avatar
Altera_Forum
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13 years ago

You need to create a generated clock that has the PLL output as the source and the clock output pin of the FPGA as the target. Then, constrain your I/O relative to this generated clock. Don't add any manual delays or inversions between the PLL and the output pin. Instead, use the PLL configuration to get the correct timing and phase.