Timequest - SSO generated output clocks

Your DDIO component will be reduce to a simple inverter, as the registers have constant outputs.

Even if it weren't, the registers uTco would not have an impact in timing, as the register's outputs are constant.

Drop the DDIO component and use a simple inversion to get an inverted clock at clk_out.

TimeQuest does know to account for propagation delay in clocks.

You just need to use "create_generated_clock -source $pllClockOut -invert [get_ports clk_out]" and it will correctly account for the delay between the PLL and the FPGA pin.

BTW, your syntax for creating a derived clock was wrong. The -source parameter must be a clock, not a net/register/pin/port.