Timequest - SSO generated output clocks

Thanks TrueBlue, that certainly is a valid alternative method for setting up a source synchronous bus although it is more demanding of pll resources and potentially has more variability from compile to compile (the delay between the PLL output and the pin).

Assuming that I didn't want to change the way that the output clock was generated, I am still interesting in knowing how one would define an output clock that it is derived from a register output.

Perhaps the output_delay timing model is not suitable in this instance and I would be better served just treating the clk_out as a signal and constraining the max skew between the databus and the clk_out (if the clock DDIO component is in an IO cell and all of the data bits are in IO cells then their tcos should be pretty well defined and close together?). There would be no generated output clock or concept of Tsu and Th relative to this. But if the clk_out is sent off chip with a minimum of skew relative to the data then can I therefore infer that I have a timing window of "Tperiod - 2*Tskew"?

Alternatively, I have seen the reference_pin command used but I wasn't very successful in implementing this...