Altera_Forum
Honored Contributor
14 years agoTimequest - specify different output delays for different paths
Hi
I am trying to interface to a bus which has different timing requirements for clock to bus driven and clock to data. It allows a short time for clock to data but a much longer time for the tristate buffers to turn on. The data register and the output enable register must be on the same clock. Does anyone know how to express this in Timequest? It works in the old timing analyzer with the following assignments:
set_instance_assignment -name TCO_REQUIREMENT "6 ns" -from "data_reg" -to "data_pin
set_instance_assignment -name TCO_REQUIREMENT "14 ns" -from "enable_reg" -to "data_pin
But in Timequest, there does not appear to be a way to specify the source register with set_output_delay.