Timequest - Constrating Centre-Aligned SDR

Tried the report_timings commands you posted and it did actually give me something useful this time. I see two hold paths, one with a relationship of -6.25ns with 3.84ns of slack (good), but also a second path which has a relationship of 0ns and -2.66ns of slack.

I think I am right in assuming this second path (the one which is violated) is actually a false path, because it seems to relate the falling edge of the launch clock (the clock driving the DDIO block) with the rising edge of the latch clock (adc_refclk_out). So I should probably cut timing paths between the falling edge of the internal one and the rising edge of the external one given that I actually clock the same data out on both rising and falling edges of the launch clock.