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Altera_Forum's avatar
Altera_Forum
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15 years ago

Time Quest SDC Command

Hi,

I have an input clock that I want to bring through the FPGA and send directly to an output. I also want to constrain some data outputs against that clock. I am having difficulty getting TQ to accurately report the delay on that clock as it goes through the FPGA.

I used create generate clock for the output and then setup out delay using the generated clock, but the clock delay is not present (no delay) in the data required path.

Any help would be appreciated.

Best regards,

Robert

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    What you've described sounds like the right way to do it. Are there any warning messages? The one I would expect is that it couldn't find a path from the master clock(input) to the generated clock(output) and hence the latency would be 0ns. An example might be if you're going through a ripple clock register before sending the clock out, or somehting like that(which would be solved by adding a generated clock to the ripple clock register).

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Also, make sure you're running report_timing with the -detail set to full_path. Otherwise the clock tree is reported as a single lump sum value, so it wouldn't look like you're seeing the whole path. I don't think this is your issue but just throwing it out there as an idea.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you for the tip on the full path timing--that answers a lot of questions!