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Altera_Forum's avatar
Altera_Forum
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13 years ago

Time delay simulation

Hi,

My question might be too newbie. But (trust me) I have searched for the solution of this problem in Google and this forum but found to answer.

I have Quartus II 9.1 and would like to simulate this Verilog code but still in vain:

module MyClock(clk);

output clk;

reg clk;

`timescale 10ms/1ms

initial

clk = 0;

always

begin

# 1 clk = ~clk;

end

endmodule

Quartus II 9.1 just gives X-es (undefined / don't care) in the simulation report. The code is supposed to produce a clock signal with 20ms period. This code (or similar) is available in many sites so I assumed it is correct.

Bottom line is I have trouble to simulate anything to do with time delays indicated by "#" and timescale directive.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    This code may simulate in a 3rd party simulator, but it will not synthesize in an Altera device with Quartus II. You have no inputs into the device, and you cannot create an output clock without an input clock in Altera devices.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks for the reply.

    So Altera products doesn't handle design without input. Does this mean any code with specific delay like:

    begin

    # 10 a <= b;

    end

    won't work also?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    No, that won't work either. Nor in Quartus nor in other synthesis tools.

    Synthesis tools only support a Verilog subset, which describes things that can be synthesized into actual hardware (logic gates, flip-flops, SRAM blocks, etc).

    The rest, the synthesis tools either ignore or yield an error.

    Your problem is that you're using Quartus to synthesize (compile) your MyClock and then using Quartus' internal simulator to simulate it.

    However, MyClock isn't synthesizable and Quartus is reducing it to an empty design with a dangling output.

    And when the simulator tries to simulate that, you get "X" as the output.

    The full set of the Verilog (or VHDL) language can only be used for simulation, using HDL simulators such as Modelsim.

    You can find a free version here: https://www.altera.com/download/software/quartus-ii-we (follow the Modelsim Altera Starter link).

    With such simulator, MyClock simulates just fine.