Time delay simulation

No, that won't work either. Nor in Quartus nor in other synthesis tools.

Synthesis tools only support a Verilog subset, which describes things that can be synthesized into actual hardware (logic gates, flip-flops, SRAM blocks, etc).

The rest, the synthesis tools either ignore or yield an error.

Your problem is that you're using Quartus to synthesize (compile) your MyClock and then using Quartus' internal simulator to simulate it.

However, MyClock isn't synthesizable and Quartus is reducing it to an empty design with a dangling output.

And when the simulator tries to simulate that, you get "X" as the output.

The full set of the Verilog (or VHDL) language can only be used for simulation, using HDL simulators such as Modelsim.

You can find a free version here: https://www.altera.com/download/software/quartus-ii-we (follow the Modelsim Altera Starter link).

With such simulator, MyClock simulates just fine.