TI ADC to HSMC adaptor, pin placement error

Quartus is checking the said IO pin distance rule to assure the signal integrity of the fast differential IO signals. On condition, that the I2C lines are not active during normal ADC operation and thus can't cause interferences, you can make Quartus ignore this rule. This is achieved by setting a TOGGLE_RATE of "0 MHZ" for the SDATA FPGA pin, in the pin planner or assignment editor.