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Altera_Forum
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15 years ago

TI ADC to HSMC adaptor, pin placement error

I'm using a TI ADS62P22 12-bit parallel ADC. I have it connected to the Cyclone III development board via the ADC to HSMC adapter board. Looking at the data sheet from TI is was able to map the inputs/outputs from the ADC to the pin placements on the Cyclone III Development board for the HSMA slot. Upon compilation, Quartus is giving me an error:

Error: Pad 94 of non-differential I/O pin 'HSMA_SDA' in pin location AC1 is too close to pad 91 of differential I/O pin 'ADC_DATA[0]' in pin location Y4 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.

Error: Pad 94 of non-differential I/O pin 'HSMA_SDA' in pin location AC1 is too close to pad 92 of differential I/O pin 'ADC_DATA[0](n)' in pin location Y3 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.

Error: Pad 94 of non-differential I/O pin 'HSMA_SDA' in pin location AC1 is too close to pad 90 of differential I/O pin 'ADC_DATA[5](n)' in pin location U5 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.

I'm confused what to do at this point, the manual specifically has the SDATA going to pin 33, or AC1 of HSMC A on the dev board. Is there something I'm missing?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Quartus is checking the said IO pin distance rule to assure the signal integrity of the fast differential IO signals. On condition, that the I2C lines are not active during normal ADC operation and thus can't cause interferences, you can make Quartus ignore this rule. This is achieved by setting a TOGGLE_RATE of "0 MHZ" for the SDATA FPGA pin, in the pin planner or assignment editor.