the throughput of ddr2 decrease after adding a pipeline bridge！

Hi,

Thanks for your reply!

I have checked the setting of the pipeline bridge. Everything seems to be what you said. I have enable the burst option, and tried burst size of 8,16,32, while no improvment occured! As to the clock, only one clock exited in the SOPC system, so it won't be wrong!

In my SOPC system, two avalon master would access to the ddr2 controller, that's nios processor and vga module. It's a pretty simple design.

I have attached my quartus project below, would you please be so kind to download the design and check for me？

I have also saved a picture may be useful in the root directory as "timming.bmp", which containing the signals i grabbed by signaltap.