the throughput of ddr2 decrease after adding a pipeline bridge！

No you shouldn't loose a lot of bandwidth, especially with bursts and pipelined transfers. Double click on the pipeline bridge and check that "allow bursts" is enabled. Set the burst size to the required value (at least same size as the master).

Check also that you are using the exact same clock on the pipeline bridge and the masters/slaves it is connected to. Clock crossing mechanisms can also reduce latency.

You are on the right track, adding pipeline bridges is the best way to increase your system Fmax, especially with so many masters connected to one slave. Adding another pipeline bridge between the CPU's data/instruction masters and its jtag_debug_module also helps.