SimonRavn
New Contributor
New ContributorThe Tempterature Sensor IP Introduces a Synchronous Clock That Breaks Timing Requirements
We have just added the "Temperature Sensor Intel® FPGA IP" (based on the "Intel® Stratix® 10 ADC") to a large design to be able to monitor the FPGA die's core temperature while it is running. However...
For anyone that have a similar issue in the future, this part of our timing problems with the temp sensor was resolved by getting the Timing Analyzer to write a new .sdc file for the project as that combines all previously given .sdc file constraints into one, in which we could find the generated create_clock constraint used for the altera_int_osc_clk clock. In our case it was:
create_clock -name {altera_int_osc_clk} -period 4.000 -waveform { 0.000 2.000 } [get_nodes {*|intosc|oscillator_dut~oscillator_clock}]
